PLC based on single chip microcomputer and CPLD backplane bus interface chip design - agreement Applications - embedded design

abstract: the design of a set of PLC backplane bus protocol interface based on CPLD chip, the backplane bus protocol chip can distinguish between PLC of periodic and aperiodic data. Introduced in detail through the Verilog HDL language design, protocol state machine frame controller, FIFO controller, the process of 25 MHZ backplane bus work under the stable test results verify the feasibility of protocols chip design.

programmable logic controller ( PLC) Host is support extension module connected through the backplane bus and the backplane bus is between the host and the I/O extension module of PLC high-speed data access, support between host and extension module I/O data refresh. The back of the bus technology determines the I/O of the PLC products extension ability, is the core of the design and manufacture technology of PLC. At present, most PLC backplane bus is realized by using serial communication technology, serial bus wire, low hardware cost less, compared with a parallel bus is not susceptible to interference, serial bus can improve in the rough factory automation equipment reliability and industrial environment. Optional types used in serial communication technology including the I2C, UART, SPI, USB and Ethernet, etc. , in general, a lot of PLC controller as the main chip microcontroller itself is integrated with the peripheral components. But single chip microcomputer internal integration of I2C, UART, SPI peripheral communication speed too slow, cannot satisfy the requirement of the backplane bus communication speed. USB and Ethernet communication speed, though soon because they are a generic interface, communication protocol processing at MCU intervention of single-chip microcomputer data processing speed slower, so the overall communication is still very slow. A large thousands of point collection of PLC I/O data of time generally less than 1 ms, to meet the requirements of such a high speed communication must design the backplane bus.

1 backplane bus works

as shown in figure 1, based on the back of the bus data communication process is as follows:

( 1) The PLC host command sent by host protocol chip to the backplane bus; ( 2) From the protocols chip MCU receives the command for extension module, a certain extension module microcontroller make response, through the reply from machine protocol chip data sent to the backplane bus; ( 3) Host protocol chip received response data, and sent to the PLC host microcontroller. Figure 1

backplane bus communication diagram

PLC host to the back of the bus data can be divided into two types: one kind is to refresh the data, I/O is cyclical, very frequent data exchange; Another kind is diagnostic data, aperiodic, appear less chance.

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